FPGA Pattern Lock With Time-Delayed Verification

Aug 29, 2025 by RICHARD 49 views

Hey guys, let's dive into building a super cool FPGA pattern lock system! This project is going to be awesome because we'll be using a Cyclone IV FPGA, some pushbuttons, an LED, and of course, some Verilog code. The goal? To create a secure system where you enter a secret pattern of button presses, and if you get it right, the system unlocks. But we're not stopping there; we're adding a time-delayed verification feature to spice things up. This means the system will give you some extra time before it locks the pattern. This is the perfect time for you to think about that pattern you created and make sure you have the right pattern. Pretty neat, right? So, buckle up, and let's get started! This project is going to be a blast, and you'll learn a ton about FPGAs, Verilog, and digital design principles. We'll walk through everything step by step, so even if you're new to FPGAs, you'll be able to follow along. Ready to get started with this fun project? Let's jump right in!

Understanding the FPGA Pattern Lock Concept

Okay, so before we jump into the code, let's make sure we're all on the same page about how this FPGA pattern lock system will work. Essentially, we're building a digital lock that responds to a sequence of button presses – a pattern. Think of it like the lock on your phone, but instead of swiping, you're tapping buttons. Here's the breakdown:

Input: We'll have four pushbuttons. Each button represents a different element in our pattern. For instance, you might define Button 1, Button 2, Button 3, and Button 4. The order in which you press these buttons forms the secret pattern. So, if you press Button 1, then Button 3, then Button 2, your pattern is 1-3-2. Easy peasy!
Pattern Storage: The FPGA will need to remember the secret pattern. We'll hardcode this pattern into the Verilog code. You can change this anytime you want to make it a different pattern.
Pattern Matching: When a user enters a pattern, the system compares it to the stored secret pattern. This is where the magic happens. The FPGA's logic will analyze the sequence of button presses and compare them against the predetermined pattern.
Output: If the entered pattern matches the secret pattern, the system unlocks. We'll use an LED to visually indicate this – maybe the LED turns on. If the pattern is incorrect, the LED stays off or flashes, indicating failure.
Time-Delayed Verification: This is our special sauce! Before the pattern is locked, the system will provide a small amount of time before checking if the pattern is correct. The time is set and adjusted in the Verilog code. This gives the user time to verify the pattern before the system responds. This is a safety feature. A user has more time to think before the lock does its job.

Now, how does all this translate into Verilog code? That's what we'll explore next! But first, let's get into the setup.

Hardware Components and Setup

Before diving into the code, let's talk about the hardware you'll need. We're building this project around a Cyclone IV FPGA, which is a pretty common and versatile platform for digital design. Here's what you'll need:

Cyclone IV FPGA Development Board: Any development board with a Cyclone IV FPGA will work. There are many options available, so choose one that fits your budget and needs. Make sure it has enough GPIO (General Purpose Input/Output) pins to connect the buttons and LED.
Four Pushbuttons: These will be our inputs. You'll need four momentary pushbuttons. These are simple on/off switches that close the circuit when pressed and open when released. They are really easy to get, which is great.
One LED: This will be our output, the visual indicator of the lock status. You'll need a standard LED and a current-limiting resistor (usually around 220 ohms) to protect the LED from burning out. A simple circuit will allow the led to light up.
Connecting Wires: Jumper wires or breadboard wires to connect the components to the FPGA board.
Breadboard (Optional): A breadboard can make connecting the components easier, especially if you're a beginner. It helps you organize your circuit.
Power Supply: The FPGA development board will usually require a power supply. Make sure you have the right one for your board.

Once you have the components, the hardware setup is fairly straightforward. You'll need to connect the pushbuttons and LED to the FPGA board. Here's a general idea:

Connect Pushbuttons: Connect each pushbutton to a separate GPIO pin on the FPGA. These pins will be configured as inputs in your Verilog code. We will set up a simple circuit to get the signal to the FPGA.
Connect LED: Connect the LED (with the current-limiting resistor in series) to another GPIO pin on the FPGA. This pin will be configured as an output in your Verilog code. This will light up the LED when the pattern is correct.
Ground: Make sure to connect all the components to the ground of your FPGA board.

Remember to consult the documentation for your FPGA development board to identify the specific GPIO pins available and how to connect the components safely. Alright, now that we've covered the hardware, let's talk code! Remember to check the pinout diagrams from the FPGA. We will get to the Verilog Code soon.

Verilog Code for the Pattern Lock System

Alright, guys, let's get down to the exciting part – writing the Verilog code! This is where we bring our FPGA pattern lock system to life. We'll break down the code into logical modules, explaining each part as we go. Here is the basic design:

module pattern_lock (
 input clk, // Clock signal
 input rst, // Reset signal
 input btn1, btn2, btn3, btn4, // Pushbutton inputs
 output reg led // LED output
);

 // Parameters
 parameter PATTERN_LENGTH = 3; // Length of the pattern
 parameter CORRECT_PATTERN = 3'b101; // The correct pattern (e.g., 1-3-1)

 // Internal signals
 reg [2:0] pattern_in; // Input pattern
 reg [2:0] pattern_count; // Pattern counter
 reg pattern_valid; // Pattern validity flag
 reg [31:0] timer_count; // Timer counter for time delay
 parameter TIMER_MAX = 50000000; // Timer max value (adjust for time delay)

 // Pattern input logic
always @(posedge clk or posedge rst) begin
 if (rst) begin
  pattern_in <= 0;
  pattern_count <= 0;
  pattern_valid <= 0;
  timer_count <= 0;
  led <= 0;
 end else begin
  if (pattern_count < PATTERN_LENGTH) begin
   if (btn1) begin
    pattern_in[pattern_count] <= 0;
    pattern_count <= pattern_count + 1;
   end else if (btn2) begin
    pattern_in[pattern_count] <= 1;
    pattern_count <= pattern_count + 1;
   end else if (btn3) begin
    pattern_in[pattern_count] <= 2;
    pattern_count <= pattern_count + 1;
   end else if (btn4) begin
    pattern_in[pattern_count] <= 3;
    pattern_count <= pattern_count + 1;
   end
  end

  // Time delay before checking the pattern
  if (pattern_count == PATTERN_LENGTH) begin
   if (timer_count < TIMER_MAX) begin
    timer_count <= timer_count + 1;
   end else begin
    pattern_valid <= (pattern_in == CORRECT_PATTERN);
    timer_count <= 0;
    pattern_count <= 0;
   end
  end else begin
   timer_count <= 0;
  end

  // LED control
  led <= pattern_valid;
 end
end

endmodule

Code Explanation

Module Declaration: We start by declaring the module named pattern_lock. This is the top-level module that encapsulates all the logic. It defines the inputs and outputs of our system. The inputs include the clock signal (clk), reset signal (rst), and the four button inputs (btn1, btn2, btn3, btn4). The output is the LED (led).
Parameters: We define two important parameters: PATTERN_LENGTH and CORRECT_PATTERN.
- PATTERN_LENGTH sets the length of the button pattern (e.g., 3 for a 3-button pattern). You can adjust it to create longer or shorter patterns.
- CORRECT_PATTERN defines the correct pattern. This is the secret key. In the example, we set it to 3'b101, which means Button 1, then Button 3, then Button 1 (assuming the buttons are numbered from 0 to 3).
Internal Signals: We declare several internal signals: pattern_in to store the entered pattern, pattern_count to track the number of button presses, pattern_valid to indicate whether the pattern is correct, and timer_count to implement the time delay.
Pattern Input Logic: The always @(posedge clk or posedge rst) block describes the behavior of the system with respect to the clock and reset signals.
- Reset: When the reset signal (rst) is high, we initialize all internal signals to their default values.
- Button Press Detection: Inside the if (pattern_count < PATTERN_LENGTH) block, the code checks for button presses. When a button is pressed, the corresponding value is added to the pattern_in register, and the pattern_count increments. This part basically captures the button presses in the right order. Remember to adjust the numbers accordingly based on the pattern you want to set.
Time Delay: After the user inputs the full pattern, we start the time delay. This is achieved using timer_count. The TIMER_MAX parameter determines the length of the delay. During the delay, the system does not yet check the pattern; it waits. This delay gives the user some time to ensure that the right pattern is in place.
Pattern Validation: After the time delay, the system checks if the entered pattern_in matches the CORRECT_PATTERN. If they match, the pattern_valid signal is asserted.
LED Control: Finally, the LED output is controlled by the pattern_valid signal. If pattern_valid is high, the LED turns on, indicating that the correct pattern was entered. We control it in a way that makes the led turn on or off.

Implementing the Time-Delayed Verification Feature

Alright, let's add that cool time-delayed verification to our FPGA pattern lock system! We've already laid the groundwork in the Verilog code by including a timer_count and a TIMER_MAX parameter. Now, let's talk about how we can tweak the code to make this feature really shine.

The Timer: The core of the time-delayed verification is a timer. We use a counter (timer_count) that increments with each clock cycle. The TIMER_MAX parameter determines how long the timer counts before triggering the verification. The TIMER_MAX needs to be calculated so that the delay can work. The delay time is determined by the speed of the clock signal.
Time Delay Logic: The time delay is implemented within the always block. The code checks if the pattern_count has reached PATTERN_LENGTH, which means the user has entered the entire pattern. Once the full pattern is entered, the timer starts counting. The system waits for the timer to reach the TIMER_MAX value.
Verification After Delay: Once the timer reaches TIMER_MAX, the code checks if pattern_in matches CORRECT_PATTERN. If they match, the pattern_valid signal is set to high, turning on the LED. If the pattern doesn't match, the LED stays off, and the system resets, ready for a new pattern entry.
Fine-tuning the Delay: The time delay is controlled by the value of TIMER_MAX and the frequency of the clock signal (clk). To adjust the delay, you can modify the value of the TIMER_MAX parameter. A larger TIMER_MAX results in a longer delay, and a smaller TIMER_MAX leads to a shorter delay. The clock's frequency also impacts the delay, which is essential.

Adjusting the Timer and Testing

Here's a tip: Start with a small TIMER_MAX value to test the functionality. Then, gradually increase the value until you find a delay that feels right for your needs. Compile, program, and test your design on your FPGA board. Make sure you understand how the timer works and what values are best for it.

Simulation and Testing

Let's get into the simulation and testing phases of your FPGA pattern lock system. Simulation allows you to test your Verilog code without using the physical FPGA board. It's super helpful for catching bugs, verifying the pattern, and ensuring your design works as intended. Testing, on the other hand, involves actually using the FPGA board to test the system. This is very important, as well.

Simulation Steps

Choose a Simulation Tool: There are many simulation tools, like ModelSim, which are industry-standard. You will need to get this before starting the simulation.
Create a Testbench: A testbench is a Verilog module that simulates the environment of your design. You will need to create a testbench. Inside the testbench, you'll instantiate your pattern_lock module and simulate the inputs (clock, reset, button presses) and monitor the outputs (LED).
Write Test Cases: In the testbench, write test cases to simulate different scenarios. For instance:
- Correct Pattern: Simulate pressing the buttons in the correct sequence and observe the LED turning on after the delay.
- Incorrect Pattern: Simulate entering an incorrect pattern and confirm that the LED does not turn on.
- Reset: Simulate a reset and ensure the system clears the entered pattern.
- Time Delay: Verify the timing by observing the LED turning on after the programmed delay period.
Run the Simulation: Run the simulation. The simulation tool will execute your testbench and display the waveforms of all signals, allowing you to analyze the behavior of your design.

Testing on the FPGA Board

Compile and Program the FPGA: After simulation, compile your Verilog code using your FPGA development software (e.g., Quartus Prime for Altera). This will create a bitstream file, which you'll then use to program the FPGA board.
Connect Hardware: Connect your pushbuttons, LED, and any other hardware components to the FPGA board, as described in the hardware setup section.
Test the Pattern Lock: Press the buttons to enter the pattern. Watch the LED to indicate the result.
- Enter the correct pattern. After the delay, the LED should light up.
- Enter an incorrect pattern. The LED should not light up.
- Experiment with different patterns and timings to ensure everything works as intended.
Troubleshooting: If the system doesn't work, review your code, simulation results, and hardware connections. Make sure everything is connected correctly and that you have the correct pattern stored in your Verilog code.

Enhancements and Further Learning

Let's add some more cool features to make your FPGA pattern lock system even better and explore some ways you can expand your knowledge! Here are some ideas:

Multiple Patterns: Implement the option for different secret patterns. This would make the system more versatile.
Pattern Length: Allow users to select the pattern length. You could add a setting with dip switches or configuration inputs.
Error Handling: Display an error message or flash the LED in a specific way if the wrong pattern is entered. This gives the user feedback.
Security Features: Add features to prevent brute-force attacks, such as a lockout timer after several failed attempts.
Display: Display the pattern entered on an LCD or seven-segment display. This will show the user what they've entered.
Real-world Applications: Think about where such a lock might be useful. Imagine it for access control, secure devices, or even as a cool project for your home.
Learn more about FPGAs: Dive deeper into topics like:
- Finite State Machines (FSMs): FSMs are fundamental in digital design. They can manage states, making your design much more organized. They are very important for your project.
- Clock Domain Crossing (CDC): CDC is an advanced topic dealing with signals that cross between clock domains. CDC is very important, so make sure you are using it.
- Hardware Description Languages: Learn more about Verilog and VHDL, the two main hardware description languages.
Read and Experiment: Explore different designs and code examples. Try modifying the existing code to add new functionality. The more you experiment, the better you'll become!

Conclusion

Alright, guys, we've come to the end of this exciting journey of building an FPGA pattern lock system with time-delayed verification! We've covered the fundamentals of designing the system, writing Verilog code, adding a timer, simulating the design, and testing it on an FPGA board. Remember that the fun doesn't stop here!

This project is an excellent starting point for anyone looking to learn about FPGAs and digital design. With a little bit of effort, you can modify and expand this project to create more complex and versatile systems. So, keep experimenting, keep learning, and most importantly, keep having fun. Until next time, happy coding! Your FPGA journey has just begun! Remember that practice is key. Experiment and expand on what you have learned today! I hope you enjoyed it. Goodbye!